The development of resonant-tunneling semiconductor devices has been motivated largely by the desire for increased miniaturization, functional density, and operating speed in electronic devices as designed for use in a variety of digital and analog circuits. Among proposed devices are two-terminal devices as disclosed, e.g., by
A. A. Lakhani et al. "Combining Resonant Tunneling Diodes for Signal Processing and Multilevel Logic", Applied Physics Letters, VOl. 52 (1988), pp. 1684-1685;
A. A. Lakhani et al, "Eleven-bit Parity Generator with a Single, Vertically Integrated Resonant Tunneling Device", Electronics Letters, Vol. 24 (1988), pp. 681-683;
R. C. Potter et al, "Three-dimensional Integration of Resonant Tunneling Structures for Signal Processing and Three-state Logic", Applied Physics Letters, Vol. 52 (1988), pp. 2163-2164; and
S. Sen et al., "New Resonant-Tunneling Devices with Multiple Negative Resistance Regions and High Room-Temperature Peak-to-Valley Ratio", IEEE Electron Device Letters, Vol. 9 (1988), pp. 402-404.
Proposed also are three-terminal devices as disclosed, e.g., by Electron Transistor (RHET)", Japanese Journal of Applied Physics, Vol. 24 (1985), pp. L853-L854;
F. Capasso et al., "Quantum-Well Resonant Tunneling Bipolar Transistor Operating at Room Temperature", IEEE Electron Device Letters, Vol. EDL-7 (1986), pp. 574-576;
F. Capasso et al, "Resonant Tunneling Gate Field-Effect Transistor", Electronics Letters, Vol. 23 (19878), pp. 225-226; and in
U.S. Pat. No. 4,712,121, "High-Speed Semiconductor Device", issued Dec. 8, 1987 to N. Yokoyama.
While such disclosed three-terminal resonant-tunneling devices have single-peak current-voltage characteristics, the invention as described below is motivated by the desire for a transistor having multiple-peak characteristics.